Senior Silicon Validation Engineer

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience developing stress tests, silicon validation frameworks, or related infrastructure. Experience in bench level validation and debug. Experience with lab equipment such as Oscilloscopes, Digital Multimeters (DMM), Logic analyzers etc. Experience programming in C/C++/Assembly. Experience scripting in Python/Perl/Tcl. Preferred qualifications: Experience with complex system debug, embedded operating systems, or bare metal programming. Experience executing tests on emulation/field programmable gate array (FPGA) and Silicon platforms. Experience with Joint Test Action Group (JTAG) debuggers (e.g., Lauterbach). Experience with Power management IC validation and Power related validation. Experience with Post Silicon debug. Proficiency in Hardware/Software interface with excellent debugging skills. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google. Responsibilities Plan, develop, and execute tests to validate hardware IP blocks and integration at the system level. Validate design on pre-silicon and post-silicon platforms. Interface with Software, Architecture, Design, and Design Verification (DV) teams to create test plans. Support silicon debug and field failures.