Senior FPGA Prototyping Engineer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a Senior FPGA & Silicon Bring-up Engineer to accelerate the development of next-generation communications ASICs. You will own FPGA prototyping, firmware enablement, first-silicon bring-up, and hardware validation, serving as the bridge between ASIC design, firmware, software, and system integration. This role spans the entire silicon lifecycle from pre-silicon FPGA platforms that enable early hardware/software integration to post-silicon debug, interface validation, and automated test infrastructure. Responsibilities Develop FPGA-based prototypes to enable early ASIC integration, firmware development, and system validation. Build hardware platforms that allow software and firmware teams to develop before first silicon. Support first-silicon bring-up, debug, and functional validation. Develop automated validation infrastructure for silicon characterization and regression testing. Configure and validate digital interfaces including high-speed Ethernet SerDes, SPI, UART, GPIO, and other peripheral interfaces. Develop FPGA-based traffic generators, protocol checkers, and test applications for interface validation. Debug issues spanning RTL, firmware, software, FPGA prototypes, and silicon using simulation and laboratory instrumentation. Collaborate closely with ASIC Design, Verification, Firmware, Software, Systems, and DFT teams to accelerate product development. Qualifications BS or MS in Electrical Engineering, Computer Engineering, or related field. 5+ years of FPGA development experience using Verilog/SystemVerilog and AMD/Xilinx FPGA tools. Strong understanding of ASIC development and digital system architecture. Experience with FPGA prototyping for ASIC development. Experience with firmware/software enablement and hardware bring-up. Strong hardware debugging skills using JTAG, oscilloscopes, logic analyzers, and protocol analyzers. Proficiency with Python and scripting for automation and test infrastructure. Nice to Have Experience with networking, communications, or satellite systems. Experience with embedded processors (ARM or RISC-V). Experience working with hard real-time embedded systems (bare-metal or RTOS). Experience validating high-speed digital interfaces, including Ethernet and SerDes protocols, SPI, and UART. Experience with silicon bring-up using JTAG, logic analyzers, and oscilloscopes. Compensation and Benefits: Base salary range for this role is $120,000 – $225,000 + equity in the company Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid paren…