Senior/Engineer STPG Product Engineering - Probe

**Our vision is to transform how the world uses information to enrich life for all.** Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. **Job Description Summary** The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM). This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements. The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle. **Career Growth & Impact** - Direct ownership of probe strategy and quality outcomes across the product lifecycle. - Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems. - Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering. **Key Responsibilities** **Probe Coverage Strategy & Ownership** - Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands. - Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead. - Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test. - Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans. **Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness** - Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging. - Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage. - Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk. - Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning). **First Silicon Bring‑Up & Device Characterization** - Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups. - Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy. - Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content. - Provide early silicon learning to accelerate probe flow stabilization and yield ramp. **Yield, Quality & Reliability Enablement** - Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe. - Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams. - Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently. **Test Efficiency & Cost Optimization** - Drive test e…