Product Application Engineer positions focus on delivering results in their domain. This page aggregates open Product Application Engineer roles and what employers typically expect.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Astera Labs Firmware Product Application Engineer , you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will help enable Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — assisting with firmware bring-up, validation, and customer issue resolution from early silicon through production ramp. You will help to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products. This position is required onsite in San Jose, CA. Key Responsibilities Assist with customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems Assist with end-to-end firmware validation of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to help deliver firmware releases and customer collateral on schedule Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind! Authorized to work in the US and available to start immediately Required Experience Proficiency in C for embedded firmware development in RTOS environments Proficiency in Python for scripting, test automation, and diagnostic tooling Knowledge with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems Knowledge of developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences. Preferred experience Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error han…