Mts Deg Design Verification positions focus on delivering results in their domain. This page aggregates open Mts Deg Design Verification roles and what employers typically expect.
**Our vision is to transform how the world uses information to enrich life for *all*.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Job Summary** As an MTS Design Verification Engineer, you will serve as a technical leader driving innovation in DRAM verification for advanced memory products. This role focuses on leading design and verification strategy, influencing key technical decisions, and ensuring high-quality, functionally correct, and scalable memory solutions. You will collaborate with global teams, guide methodology improvements, mentor engineers, and act as a domain expert to support next-generation DRAM technologies. **Responsibilities** - Lead DRAM verification innovation, driving key technical decisions, architecture, and strategy during product execution - Collaborate with global teams to define and implement best-known methods for verification and product development - Drive verification planning, coverage closure, and silicon debugging for advanced DRAM products - Evaluate and implement new tools, methodologies, and flows to improve verification efficiency and quality - Mentor engineers and provide technical leadership while contributing expert guidance to senior leadership teams **Minimum Qualifications** - Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field - 8+ years of experience in DRAM/memory or advanced CMOS verification - Strong circuit analysis and debug skills at the transistor level — able to root-cause behavior, not only at the testbench level - Experience with simulation tools such as HSPICE, Finesim, Verilog, or SystemVerilog - Deep understanding of CMOS fundamentals and semiconductor design principles - Demonstrated leadership, problem-solving, and ability to collaborate across multiple functions **Preferred Qualifications** - Advanced degree (Master’s or PhD) in Electrical Engineering or related field, with equivalent experience considered - Experience with UVM, mixed-signal verification, and advanced DRAM architectures (e.g., DDR5 or beyond) - Strong background in verification methodology development and coverage strategies - Experience mentoring engineers and leading technical initiatives across teams - Recognition as an authority in DRAM build or verification domains - Strong programming skills (Python preferred) with ability to apply AI-assisted tools (e.g., ClaudeCode) to improve EDA automation, data analysis, and build efficiency **Responsibilities** - Lead DRAM design and/or verification innovation, driving technical strategy and execution. - Collaborate with global teams to develop and share best-known methods across product lines. - Drive circuit improvement, verification planning, coverage closure, and silicon debug. - Define and implement tools, methodologies, and automation to improve quality and efficiency. - Provide technical leadership in mixed-signal simulation, validation, and signoff strategy for DDR5 and beyond. - Mentor engineers and serve as a DRAM authority for senior leadership. **Minimum Qualifications** - Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience. - Strong expertise in DRAM design and/or verification for advanced memory products. - Hands-on experience with tools such as HSPICE, FINESIM, Verilog, and SystemVerilog. - Strong understanding of CMOS fundamentals, semiconductor design, and product development flows. - Demonstrated leadership, problem-solving, and multi-functional communication skills. **Preferred Qualifications** - Advanced degree in Electrical Engineering or related field, or equivalent experience. - Experience with UVM, mixed-signal verification, advanced DRAM architectures, and DDR5+ methodology development. - Background in verification planning, coverage strategy, debug, and silicon…