Mid Level ASIC Design Engineer

About Tensordyne Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Tensordyne is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment. About the role: As a member of Tensordyne’s ASIC team, you will be responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC.This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record-breaking computational performance at low power. Your responsibilities will be wide-ranging and run the gamut of microarchitecture design and documentation, Verilog RTL implementation, selecting and integration 3rd-party IP blocks, working closely with design verification engineers, running frontend synthesis and working with a backend team on place-and-route guidance and timing closure. Responsibilities: Author/Understand micro-architecture specifications and participate in specification and test plan reviews. Implement complex RTL designs. Integrate CPU and other relevant IPs into the CPU sub-system. Collaborate with the physical design team to resolve implementation and timing issues and to optimize power. Analyze code coverage and provide feedback to the verification team to achieve coverage closure. Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab. Required Qualifications: 3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog. Experience in IP integration, specifically CPU IP into SoC. Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation Familiarity with AMBA/APB/AXI Protocol Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C .... Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies. Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains Previous experience with timing closure at high frequencies is a plus. Interest to explore AI architectures for convolution, transformer and other kinds of workloads Self-starter and highly-motivated to work in a dynamic start-up environment. B.S. (M.S. preferred) degree in Electrical or Computer engineering. Tensordyne's culture was built on the following values that are equally important to us as business: Put people first. We only succeed when our people succeed. Ethics and integrity always; Being open, honest, and respectful of everyone. Think Big. Be ambitious and have audacious goals. Aim for excellence. Qua…