Hardware Design Engineering, Director - OEM, Silicon Validation Platforms & Rack-Scale Design - Taiwan

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are hiring a Director of Hardware Design Engineering — OEM, Silicon Validation Platforms & Rack-Scale Design to establish and lead Astera Labs' Taiwan hardware engineering center. This role serves as the primary hardware engineering hub for OEM customer engagement across Asia, while simultaneously owning the design and development of Silicon Validation Platforms (SVB/EVB) and rack-scale products (AI chassis, switch trays, CEM cards). This is a high-impact leadership role that combines three critical functions: OEM Design Enablement & Customer Support — Serving as the front-line hardware engineering partner for OEM customers in Asia (hyperscale cloud, server/switch OEMs, cable/module manufacturers) who are integrating Astera Labs silicon into their own products Silicon Validation Platform Design (SVB/EVB) — Designing and delivering the evaluation boards and system validation platforms that enable silicon bring-up, characterization, customer evaluation, and reference design seeding Rack-Scale Product Design — Designing AI chassis-class systems, switch trays, CEM cards, and system-level hardware that showcase Astera Labs' full connectivity portfolio You will build and lead a multidisciplinary hardware engineering team in Taiwan — spanning electrical/PCB design, mechanical engineering, validation, and customer applications engineering. You'll serve as the senior Astera Labs hardware engineering leader in Asia, partnering with OEM customers, ODM partners, and contract manufacturers while maintaining tight alignment with the Santa Clara-based engineering organization. Reporting to the Senior Director of Hardware Design Engineering, you'll operate with significant autonomy while ensuring strategic alignment on technology roadmap, design standards, and customer priorities. Key Responsibilities Taiwan Engineering Center Leadership Establish, build, and lead Astera Labs' Taiwan hardware engineering center as the company's primary Asia-based hub for OEM engagement, silicon platform design, and rack-scale product development Recruit, hire, and develop a high-caliber multidisciplinary engineering team in Taiwan, including: Hardware/PCB design engineers Mechanical engineers Validation engineers Customer/applications hardware engineers Lab engineers Define organizational structure, hiring roadmap, and operating model for the Taiwan center — balancing local autonomy with global alignment Establish lab infrastructure in Taiwan to support silicon platform bring-up, customer demonstrations, OEM design reviews, interoperability testing, and rack-scale system validation Drive engineering culture that emphasizes customer responsiveness, design excellence, and tight collaboration with Santa Clara headquarters Serve as the senior Astera Labs engineering leader in Asia — representing the company with customers, partners, and industry stakeholders in the region OEM Design Enablement & Customer Engagement Customer Design Support: Serve as the primary hardware engineering interface for OEM customers in Asia who are designing Astera Labs silicon (retimers, re-drivers, connectivity ASICs) into their own products Provide expert-level design review support for customer hardware designs — r…