DFT Design Engineering Director

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/). **About the Role** We are seeking an experienced **Director of Design for Test (DFT)** to lead our DFT engineering efforts for the Scorpio family of PCIe switch products. In this critical leadership role, you will define and execute the DFT strategy for complex, high-speed SerDes-based switching solutions, ensuring optimal testability, yield, and quality while enabling cost-effective manufacturing at scale. **This role requires deep expertise in advanced packaging technologies including 2.5D and 3D integration, as our products leverage cutting-edge multi-die architectures.** **Key Responsibilities** **DFT Strategy & Leadership** - Define and drive the comprehensive DFT strategy for PCIe Gen3/4/5/6 switch products with 2.5D/3D packaging - Lead and mentor a team of DFT engineers across multiple product development cycles - Collaborate with design, verification, packaging, and product engineering teams to optimize test coverage and manufacturing cost - Establish DFT best practices, methodologies, and flows for complex multi-billion transistor designs in advanced packaging configurations **Advanced Packaging DFT Architecture** - **Develop DFT strategies for 2.5D/3D heterogeneous integration architectures:** - Multi-die test access and coordination through silicon interposers - Through-Silicon Via (TSV) testing and characterization - Die-to-die interface testing and Known Good Die (KGD) strategies - Chiplet-level DFT with system-level test integration - Hybrid bonding and micro-bump interconnect testing - **Architect test access mechanisms for:** - Inter-die communication channels and high-bandwidth interfaces - HBM/DRAM interfaces in 2.5D configurations - Power delivery network testing across multiple dies - Thermal and reliability test structures - **Define pre-bond and post-bond test strategies:** - Individual die screening and KGD qualification - Stack-level testing for 3D integrated circuits - Package-level test optimization and cost reduction **Technical Execution** - Architect and implement advanced DFT features including: - Scan insertion, ATPG, and compression strategies for multi-die systems - Memory BIST (MBIST) for embedded SRAM and register files - Logic BIST (LBIST) for at-speed testing - IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG) for die-level and package-level access - IEEE 1838 (3D-DFT) standards for 3D stacked die test - High-speed SerDes BIST and loopback testing across die boundaries - Analog/mixed-signal test hooks and observability - Built-in Self-Repair (BISR) for redundancy management - Drive fault coverage targets (>99% stuck-at, >95% transition) across all dies - Optimize test time and ATE costs while maintaining quality metrics - Define and implement production test programs and diagnostic capabilities for packaged devices **Cross-Functional Collaboration** - Partner with physical design and packaging teams to optimize DFT area, timing, and package routing impact - Work with silicon validation teams to enable post-silicon debug and characterization of multi-die systems - Collaborate with manufacturing, assembly, and test engineering for seamless production ramp - Interface with OSAT partners, substrate vendors, a…