Design Verification Engineer, Intern

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines – they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone. As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent’s next-generation RISC‑V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high‑performance computing roadmap. We are looking for a minimum of 3 months for this role with the potential for extension to 6 months. This role is hybrid, based in our Boston, MA office. Who you are Pursuing a B.S. , M.S. or PhD. in Electrical Engineering, Computer Engineering, Computer Science , or a related field with a focus on digital design and verification . Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems). Familiar with HDLs such as Verilog/SystemVerilog , and interested in learning Formal verification, Cocotb, and UVM‑based verification methodologies . Comfortable working in Linux-based development environments and using scripting languages (e.g., Python, Shell, Perl ) to automate tasks. Detail-oriented problem solver who enjoys debugging complex issues , reasoning about corner cases, and working from specifications. Collaborative team member with clear communication skills, able to document work and discuss trade‑offs with RTL, architecture, and validation teams. What We Need Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards. Write and refine verification test plans from architectural and micro‑architectural specifications, with a strong focus on corner cases and coverage. Develop constrained‑random and directed tests , run regressions, and triage failures by working closely with RTL designers to root-cause issues. Analyze functional and code coverage results , identify gaps, and propose additional tests or checks to drive coverage closure. Contribute to automation and infrastructure (scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time. Partner with cross‑functional teams (architecture, design, performance, validation) to align on expected behavior and sign‑off criteria for silicon. Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build. What You Will Learn End‑to‑end SoC design and verification flow for cutting‑edge RISC‑V and AI accelerator architectures. Industry‑standard verification methodologies (SystemVerilog/UVM) , including testbench architecture, stimulus generation, and scoreboard/checker design. Hands-on experience with simulation, regression, and coverage tools used in large‑…